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2.5 v to 5.5 v, 400 a, 2-wire interface, quad voltage output, 8-/10-/12-bit dacs ad5306/ad5316/ad5326 rev. f information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent ri ghts of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2005 analog devices, inc. all rights reserved. features ad5306: 4 buffered, 8-bit dacs in 16-lead tssop a version: 1 lsb inl; b version: 0.625 lsb inl ad5316: 4 buffered, 10-bit dacs in 16-lead tssop a version: 4 lsb inl; b version: 2.5 lsb inl ad5326: 4 buffered, 12-bit dacs in 16-lead tssop a version: 16 lsb inl; b version: 10 lsb inl low power operation: 400 a @ 3 v, 500 a @ 5 v 2-wire (i 2 c?-compatible) serial interface 2.5 v to 5.5 v power supply guaranteed monotonic by design over all codes power-down to 90 na @ 3 v, 300 na @ 5 v ( pd pin or bit) double-buffered input logic buffered/unbuffered reference input options output range: 0 v to v ref or 0 v to 2 v ref power-on reset to 0 v simultaneous update of outputs ( ldac pin) software clear facility data readback facility on-chip rail-to-rail output buffer amplifiers temperature range ?40c to +105c applications portable battery-powered instruments digital gain and offset adjustment programmable voltage and current sources programmable attenuators industrial process control 1 protected by u.s. patent numbers 5,969,657 and 5,684,481. functional block diagram scl interface logic input register dac register input register dac register v out a string dac a string dac b v dd v ref b v ref a v ref c v ref d v out b power-on reset power-down logic ldac a1 a0 ldac sda gndpd ad5306/ad5316/ad5326 buffer buffer input register dac register input register dac register v out c string dac c string dac d v out d buffer buffer 02066-001 figure 1. general description the ad5306/ad5316/ad5326 1 are quad 8-/10-/12-bit buffered voltage output dacs in 16-lead tssop packages that operate from a single 2.5 v to 5.5 v supply, consuming 500 a at 3 v. their on-chip output amplifiers allow rail-to-rail output swing with a slew rate of 0.7 v/s. a 2-wire serial interface, which operates at clock rates up to 400 khz, is used. this interface is smbus-compatible at v dd < 3.6 v. multiple devices can be placed on the same bus. each dac has a separate reference input that can be configured as buffered or unbuffered. the outputs of all dacs can be updated simultaneously using the asynchronous ldac input. the parts incorporate a power-on reset circuit that ensures the dac outputs power up to 0 v and remain there until a valid write to the device takes place. the software clear function clears all dacs to 0 v. the parts contain a power-down feature that reduces the current consumption of the device to 300 na @ 5 v (90 na @ 3 v). all three parts have the same pinout, which allows users to select the amount of resolution appropriate for their application without redesigning their circuit board.
ad5306/ad5316/ad5326 rev. f | page 2 of 24 table of contents specifications ..................................................................................... 3 ac characteristics ........................................................................ 5 timing characteristics ................................................................ 6 absolute maximum ratings ............................................................ 7 esd caution .................................................................................. 7 pin configuration and function descriptions ............................. 8 ter mi nolo g y ...................................................................................... 9 typical performance characteristics ........................................... 11 functional description .................................................................. 15 digital-to-analog section ......................................................... 15 resistor string ............................................................................. 15 dac reference inputs ............................................................... 15 output amplifier ........................................................................ 15 power-on reset .......................................................................... 16 serial interface ............................................................................ 16 read/write sequence ................................................................. 16 pointer byte bits ......................................................................... 16 input shift register ..................................................................... 16 default readback conditions ................................................... 17 multiple dac write sequence ................................................. 17 multiple dac readback sequence .......................................... 17 write operation .......................................................................... 18 read operation ........................................................................... 18 double-buffered interface ........................................................ 19 load dac input ldac ............................................................. 19 power-down mode .................................................................... 19 applications ..................................................................................... 20 typical application circuit ....................................................... 20 driving v dd from the reference voltage ................................ 20 bipolar operation using the ad5306/ad5316/ad5326 ..... 20 multiple devices on one bus ................................................... 20 ad5306/ad5316/ad5326 as a digitally programmable window detector ....................................................................... 21 coarse and fine adjustment using the ad5306/ad5316/ad5326 ....................................................... 21 power supply decoupling ............................................................. 22 outline dimensions ....................................................................... 24 ordering guide .......................................................................... 24 revision history 8/05rev. e to rev. f replaced figure 22 ......................................................................... 13 changes to bipolar operation using the ad5306/ad5316/ad5326 section........................ 20 changes to ordering guide .......................................................... 24 5/05rev. d to rev. e changes to table 1............................................................................ 3 11/04rev. c to rev. d change to figure 31 ....................................................................... 16 changes to pointer byte section................................................... 16 change to figure 32 ....................................................................... 17 8/03rev. b to rev. c added a version ................................................................universal changes to features ....................................................................1 changes to specifications .......................................................2 changes to absolute maximum ratings .........................5 edits to ordering guide ..........................................................5 changes to tpc 21......................................................................... 11 added octals section to table i............................................... 18 updated outline dimensions ............................................ 19 4/01rev. a to rev. b edit to figure 6 ............................................................................... 13 edits to right/left section of pointer byte bits section...... 13 edits to input shift register section ............................................ 13 edits to figure 7.............................................................................. 13 edits to figure 8.............................................................................. 14 edits to figure 9.............................................................................. 14 edit to figure 12 ............................................................................. 16 2/01rev. 0 to rev. a 6/00revision 0: initial version
ad5306/ad5316/ad5326 rev. f | page 3 of 24 specifications v dd = 2.5 v to 5.5 v; v ref = 2 v; r l = 2 k to gnd; c l = 200 pf to gnd; all specifications t min to t max , unless otherwise noted. table 1. a version 1 b version 1 parameter 2 min typ max min typ max unit conditions/comments dc performance 3 , 4 ad5306 resolution 8 8 bits relative accuracy 0.15 1 0.15 0.625 lsb differential nonlinearity 0.02 0.25 0.02 0.25 lsb guaranteed monotonic by design over all codes. ad5316 resolution 10 10 bits relative accuracy 0.5 4 0.5 2.5 lsb differential nonlinearity 0.05 0.5 0.05 0.5 lsb guaranteed monotonic by design over all codes. ad5326 resolution 12 12 bits relative accuracy 2 16 2 10 lsb differential nonlinearity 0.2 1 0.2 1 lsb guaranteed monotonic by design over all codes. offset error 5 60 5 60 mv v dd = 4.5 v, gain = 2; see figure 4 and figure 5 . gain error 0.3 1.25 0.3 1.25 % of fsr v dd = 4.5 v, gain = 2; see figure 4 and figure 5 . lower deadband 5 10 60 10 60 mv see figure 4 ; lower deadband exists only if offset error is negative. upper deadband 5 10 60 10 60 mv see figure 5 ; upper deadband exists only if v ref = v dd and offset plus gain error is positive. offset error drift 6 ?12 C12 ppm of fsr/c gain error drift 6 C5 C5 ppm of fsr/c dc power supply rejection ratio 6 C60 C60 db v dd = 10%. dc crosstalk 6 200 200 v r l = 2 k to gnd or v dd. dac reference inputs 6 v ref input range 1 v dd 1 v dd v buffered reference mode. 0.25 v dd 0.25 v dd v unbuffered reference mode. v ref input impedance >10 >10 m buffered reference mode and power-down mode. 148 180 148 180 k unbuffered reference mode; 0 v to v ref output range. 74 90 74 90 k unbuffered reference mode; 0 v to 2 v ref output range. reference feedthrough ?90 ?90 db frequency = 10 khz. channel-to-channel isolation ?75 ?75 db frequency = 10 khz. output characteristics 6 minimum output voltage 7 0.001 0.001 v this is a measure of the minimum and maximum drive capability of the output amplifier. maximum output voltage 7 v dd ? 0.001 v dd ? 0.001 v dc output impedance 0.5 0.5
ad5306/ad5316/ad5326 rev. f | page 4 of 24 a version 1 b version 1 parameter 2 min typ max min typ max unit conditions/comments short-circuit current 25 25 ma v dd = 5 v. 16 16 ma v dd = 3 v. power-up time 2.5 2.5 s coming out of power- down mode; v dd = 5 v. 5 5 s coming out of power- down mode; v dd = 3 v. logic inputs (excluding scl, sda) 6 input current 1 1 a v il , input low voltage 0.8 0.8 v v dd = 5 v 10%. 0.6 0.6 v v dd = 3 v 10%. 0.5 0.5 v v dd = 2.5 v. v ih , input high voltage 1.7 1.7 v v dd = 2.5 v to 5.5 v; ttl and 1.8 v cmos compatible. pin capacitance 3 3 pf logic inputs (scl, sda) 6 v ih , input high voltage 0.7 v dd v dd + 0.3 0.7 v dd v dd + 0.3 v smbus compatible at v dd < 3.6 v. v il , input low voltage ?0.3 +0.3 v dd ?0.3 +0.3 v dd v smbus compatible at v dd < 3.6 v. i in , input leakage current 1 1 a v hyst , input hysteresis 0.05 v dd 0.05 v dd v see figure 20 . c in , input capacitance 8 8 pf glitch rejection 50 50 ns input filtering suppresses noise spikes of less than 50 ns. logic output (sda) 6 v ol , output low voltage 0.4 0.4 v i sink = 3 ma. 0.6 0.6 v i sink = 6 ma. three-state leakage current 1 1 a three-state output capacitance 8 8 pf power requirements v dd 2.5 5.5 2.5 5.5 v i dd (normal mode) 8 v ih = v dd and v il = gnd; interface inactive. v dd = 4.5 v to 5.5 v 500 900 500 900 a all dacs in unbuffered mode. buffered mode, extra current is typically x ma per dac, where x = 5 a + v ref /r dac. v dd = 2.5 v to 3.6 v 400 750 400 750 a i dd (power-down mode) v ih = v dd and v il = gnd; interface inactive. v dd = 4.5 v to 5.5 v 0.3 1 0.3 1 a i dd = 3 a (max) during readback on sda. v dd = 2.5 v to 3.6 v 0.09 1 0.09 1 a i dd = 1.5 a (max) during readback on sda. 1 temperature range (a, b versions): ?40c to +105c; ty pical at +25c. 2 see the terminology section. 3 dc specifications tested with the outputs unloaded. 4 linearity is tested using a reduce d code range: ad5306 (code 8 to 255); ad 5316 (code 28 to 1023); ad 5326 (code 115 to 4095). 5 this corresponds to x codes. x = deadband voltage/lsb size. 6 guaranteed by design and characterization; not production tested. 7 for the amplifier output to reach its minimum voltage, the offset error must be negative; for the amplifier output to reach it s maximum voltage, v ref = v dd , the offset plus gain error must be positive. 8 interface inactive; all dacs active. dac outputs unloaded.
ad5306/ad5316/ad5326 rev. f | page 5 of 24 ac characteristics v dd = 2.5 v to 5.5 v; r l = 2 k to gnd; c l = 200 pf to gnd; all specifications t min to t max , unless otherwise noted. table 2 . a, b versions 1 , 2 parameter 3 min typ max unit conditions/comments output voltage settling time v ref = v dd = 5 v ad5306 6 8 s 1/4 scale to 3/4 scale change (0x40 to 0xc0) ad5316 7 9 s 1/4 scale to 3/4 scale change (0x100 to 0x300) ad5326 8 10 s 1/4 scale to 3/4 scale change (0x400 to 0xc00) slew rate 0.7 v/s major-code change glitch energy 12 nv-s 1 lsb change around major carry digital feedthrough 0.5 nv-s digital crosstalk 0.5 nv-s analog crosstalk 1 nv-s dac-to-dac crosstalk 3 nv-s multiplying bandwidth 200 khz v ref = 2 v 0.1 v p-p, unbuffered mode total harmonic distortion ?70 db v ref = 2.5 v 0.1 v p-p, frequency = 10 khz 1 guaranteed by design and characterization; not production tested. 2 temperature range (a, b versions): ?40c to +105c; ty pical at +25c. 3 see the terminology section.
ad5306/ad5316/ad5326 rev. f | page 6 of 24 timing characteristics 1 v dd = 2.5 v to 5.5 v; all specifications t min to t max , unless otherwise noted. table 3. parameter 2 a, b versions limit at t min , t max unit conditions/comments t 1 2.5 s min scl cycle time t 2 0.6 s min t high , scl high time t 3 1.3 s min t low , scl low time t 4 0.6 s min t hd,sta , start/repeated start condition hold time t 5 100 ns min t su,dat , data setup time t 6 3 0.9 s max t hd,dat , data hold time 0 s min t 7 0.6 s min t su,sta , setup time for repeated start t 8 0.6 s min t su,sto , stop condition setup time t 9 1.3 s min t buf , bus free time between a stop and a start condition t 10 300 ns max t r , rise time of scl and sda when receiving 0 ns min t r , rise time of scl and sda when receiving (cmos compatible) t 11 250 ns max t f , fall time of sda when transmitting 0 ns min t f , fall time of sda when receiving (cmos compatible) 300 ns max t f , fall time of scl and sda when receiving 20 + 0.1c b 4 ns min t f , fall time of scl and sda when transmitting t 12 20 ns min ldac pulse width t 13 400 ns min scl rising edge to ldac rising edge c b 4 400 pf max capacitive load for each bus line 1 see figure 2. 2 guaranteed by design and characterization; not production tested. 3 a master device must provide a hold time of at least 300 ns for the sda signal (ref erred to the v ih min of the scl signal) to bridge the undefined region of scls falling edge. 4 c b is the total capacitance of one bus line in pf. t r and t f measured between 0.3 v dd and 0.7 v dd . scl sd a t 1 t 3 ldac 1 ldac 2 start condition repeated start condition stop condition notes 1 asynchronous ldac update mode. 2 synchronous ldac update mode. t 4 t 6 t 5 t 7 t 8 t 2 t 13 t 4 t 11 t 10 t 12 t 12 t 9 02066-002 figure 2. 2-wire serial interface timing diagram
ad5306/ad5316/ad5326 rev. f | page 7 of 24 absolute maximum ratings t a = 25c, unless otherwise noted. table 4. parameter 1 value v dd to gnd ?0.3 v to +7 v scl, sda to gnd ?0.3 v to v dd + 0.3 v a0, a1, ldac , pd to gnd ?0.3 v to v dd + 0.3 v reference input voltage to gnd ?0.3 v to v dd + 0.3 v v out a to v out d to gnd ?0.3 v to v dd + 0.3 v operating temperature range industrial (a, b vers ions) ?40c to +105c storage temperature range ?65c to +150c junction temperature (t j max) 150c 16-lead tssop power dissipation (t j max ? t a )/ ja ja thermal impedance 150.4c/w reflow soldering peak temperature 220c time at peak temperature 10 sec to 40 sec 1 transient currents of up to 100 ma do not cause scr latch-up. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution esd (electrostatic discharge) sensitive device. electrosta tic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although this product features proprietary esd protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
ad5306/ad5316/ad5326 rev. f | page 8 of 24 pin configuration and fu nction descriptions 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 v dd v out a v out b v ref b v ref a v out c ldac a0 scl sda pd v ref cv ref d v out d gnd a1 ad5306/ ad5316/ ad5326 top view (not to scale) 02066-003 figure 3. pin configuration table 5. pin function descriptions pin no. mnemonic description 1 ldac active low control input. transfers the contents of th e input registers to their respective dac registers. pulsing this pin low allows any or all dac registers to be updated if the input re gisters have new data. this allows simultaneous update of all dac outputs. alternatively, this pi n can be tied permanently low. 2 v dd power supply input. these parts can be operated from 2.5 v to 5.5 v and the supply should be decoupled with a10 f capacitor in parallel with a 0.1 f capacitor to gnd. 3 v out a buffered analog output voltage from dac a. th e output amplifier has rail-to-rail operation. 4 v out b buffered analog output voltage from dac b. th e output amplifier has rail-to-rail operation. 5 v out c buffered analog output voltage from dac c. th e output amplifier has rail-to-rail operation. 6 v ref a reference input pin for dac a. this pin can be configur ed as a buffered or an unbuffered input depending on the state of the buf bit in the input word to dac a. it has an input range from 0.25 v to v dd in unbuffered mode and from 1 v to v dd in buffered mode. 7 v ref b reference input pin for dac b. this pin can be configur ed as a buffered or an unbuffered input depending on the state of the buf bit in the input word to dac b. it has an input range from 0.25 v to v dd in unbuffered mode and from 1 v to v dd in buffered mode. 8 v ref c reference input pin for dac c. this pin can be configur ed as a buffered or an unbuffered input depending on the state of the buf bit in the input word to dac c. it has an input range from 0.25 v to v dd in unbuffered mode and from 1 v to v dd in buffered mode. 9 v ref d reference input pin for dac d. this pin can be configur ed as a buffered or an unbuffered input depending on the state of the buf bit in the input word to dac d. it has an input range from 0.25 v to v dd in unbuffered mode and from 1 v to v dd in buffered mode. 10 pd active low control input. acts as a hardware power-down option. all da cs go into power-down mode when this pin is tied low. the dac outputs go into a high impedance state. the current consumption of the part drops to 300 na @ 5 v (90 na @ 3 v). 11 v out d buffered analog output voltage from dac d. th e output amplifier has rail-to-rail operation. 12 gnd ground reference point for all circuitry on the part. 13 sda serial data line. this is used in conjunction with the scl line to clock data into the 16-bit input shift register. it is a bidirectional open-drain data line that should be pulled to the supply with an external pull-up resistor. 14 scl serial clock line. this is used in co njunction with the sda line to clock da ta into the 16-bit input shift register. clock rates of up to 400 kbps can be accommodated in the i 2 c-compatible interface. 15 a0 address input. sets the lsb of the 7-bit slave address. 16 a1 address input. sets the second lsb of the 7-bit slave address.
ad5306/ad5316/ad5326 rev. f | page 9 of 24 terminology relative accuracy or integral nonlinearity (inl) for the dac, it is a measure, in lsb, of the maximum deviation from a straight line passing through the endpoints of the dac transfer function. typical inl vs. code plots are shown in figure 6 , figure 7 , and figure 8 . differential nonlinearity (dnl) the difference between the measured change and the ideal 1 lsb change between any two adjacent codes. a specified differential nonlinearity of 1 lsb maximum ensures monotonicity. this dac is guaranteed monotonic by design. typical dnl vs. code plots are shown in figure 9 , figure 10 , and figure 11 . offset error a measure of the offset error of the dac and the output ampli- fier. it can be positive or negative. see figure 4 and figure 5 . offset error is expressed in mv. gain error a measure of the span error of the dac. it is the deviation in slope of the actual dac transfer characteristic from the ideal expressed as a percentage of the full-scale range. offset error drift a measure of the change in offset error with changes in temperature. offset error drift is expressed in (ppm of full-scale range)/c. gain error drift a measure of the change in gain error with changes in temperature. gain error drift is expressed in (ppm of full-scale range)/c. dc power supply rejection ratio (psrr) this indicates how the output of the dac is affected by changes in the supply voltage. psrr is the ratio of the change in v out to a change in v dd for full-scale output of the dac. psrr is measured in db. v ref is held at 2 v and v dd is varied 10%. dc crosstalk the dc change in the output level of one dac at midscale in response to a full-scale code change (all 0s to all 1s, and vice versa) and output change of another dac. dc crosstalk is expressed in v. reference feedthrough the ratio of the amplitude of the signal at the dac output to the reference input when the dac output is not being updated, that is, when ldac is high. reference feedthrough is expressed in db. channel-to-channel isolation the ratio of the amplitude of the signal at the output of one dac to a sine wave on the reference input of another dac. channel-to-channel isolation is measured in db. major-code transition glitch energy the energy of the impulse injected into the analog output when the code in the dac register changes state. this energy is normally specified as the area of the glitch in nv-s and is measured when the digital code is changed by 1 lsb at the major carry transition (011...11 to 100...00 or 100...00 to 011...11). digital feedthrough a measure of the impulse injected into the analog output of a dac from the digital input pins of the device when the dac output is not being updated. digital feedthrough is specified in nv-s and is measured with a worst-case change on the digital input pins (that is, from all 0s to all 1s, and vice versa). digital crosstalk the glitch impulse transferred to the output of one dac at midscale in response to a full-scale code change (all 0s to all 1s, and vice versa) in the input register of another dac. the energy of the glitch is expressed in nv-s. analog crosstalk the glitch impulse transferred to the output of one dac due to a change in the output of another dac. analog crosstalk is measured by loading one of the dacs with a full-scale code change (all 0s to all 1s, and vice versa) while keeping ldac high and then pulsing ldac low and monitoring the output of the dac whose digital code has not changed. the energy of the glitch is expressed in nv-s. dac-to-dac crosstalk the glitch impulse transferred to the output of one dac due to a digital code change and subsequent output change of another dac. this includes both digital and analog crosstalk. crosstalk is measured by loading one of the dacs with a full-scale code change (all 0s to all 1s, and vice versa) with ldac low and then monitoring the output of another dac. the energy of the glitch is expressed in nv-s. multiplying bandwidth the amplifiers within the dac have a finite bandwidth. the multiplying bandwidth is a measure of this. a sine wave on the reference (with full-scale code loaded to the dac) appears on the output. the multiplying bandwidth is the frequency at which the output amplitude falls to 3 db below the input. total harmonic distortion (thd) the difference between an ideal sine wave and its attenuated version using the dac. the sine wave is used as the reference for the dac, and the thd is a measure of the harmonics present on the dac output. thd is measured in db.
ad5306/ad5316/ad5326 rev. f | page 10 of 24 dac code actual ideal gain error plus offset error output voltage negative offset error negative offset error amplifier footroom l o w e r d e a d b a n d c o d e s 02066-004 figure 4. transfer function with negative offset dac code full scale actual ideal positive offset error output voltage gain error plus offset error upper deadband codes 02066-005 figure 5. transfer function with positive offset (v ref = v dd )
ad5306/ad5316/ad5326 rev. f | page 11 of 24 typical performance characteristics inl error (lsb) ?1.0 ?0.5 0 0.5 1.0 0 50 100 150 200 250 code t a = 25 c v dd = 5v 02066-006 figure 6. ad5306 inl ?3 ?2 ?1 0 1 2 3 inl error (lsb) 0 200 400 600 800 1000 code t a = 25 c v dd = 5v 02066-007 figure 7. ad5316 inl ?12 ?8 ?4 0 4 8 12 inl error (lsb) 2000 1500 500 1000 0 2500 3000 3500 4000 code t a = 25 c v dd = 5v 02066-008 figure 8. ad5326 inl 02066-009 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 dnl error (lsb) 0 50 100 150 200 250 code t a = 25 c v dd = 5v figure 9. ad5306 dnl ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 dnl error (lsb) 0 200 400 600 800 1000 code t a = 25 c v dd = 5v 02066-010 figure 10. ad5316 dnl dnl error (lsb) ?1.0 ?0.5 0 0.5 1.0 2000 1500 500 1000 0 2500 3000 3500 4000 code t a = 25 c v dd = 5v 02066-011 figure 11. ad5326 dnl
ad5306/ad5316/ad5326 rev. f | page 12 of 24 error (lsb) ?0.50 ?0.25 0 0.25 0.50 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 v ref (v) t a = 25 c v dd = 5v max inl max dnl min dnl min inl 02066-012 figure 12. ad5306 inl and dnl error vs. v ref ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 error (lsb) temperature ( c) 0 ?40 40 80 120 v dd = 5v v ref = 3v max inl max dnl min dnl min inl 02066-013 figure 13. ad5306 inl and dnl error vs. temperature error (% fsr) ?1.0 ?0.5 0 0.5 1.0 temperature ( c) 0 ?40 40 80 120 v dd = 5v v ref = 2v gain error offset error 02066-014 figure 14. ad5306 offset error and gain error vs. temperature ?0.6 ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 error (% fsr) 0 0.1 0.2 23 01 456 v dd (v) t a = 25c v ref = 2v gain error offset error 02066-015 figure 15. offset error and gain error vs. v dd 0 1 2 3 4 5 v out (v) 23 01 456 sink/source current (ma) 5v source 3v source 5v sink 3v sink 02066-016 figure 16. v out vs. source and sink current capability 0 50 100 150 200 250 300 i dd ( a) zero scale full scale code t a = 25 c v dd = 5v v ref = 2v 02066-017 figure 17. supply current vs. dac code
ad5306/ad5316/ad5326 rev. f | page 13 of 24 0 100 200 300 400 500 600 i dd ( a) 3.5 4.0 2.5 3.0 4.5 5.0 5.5 v dd (v) +25 c ?40c 02066-018 +105 c figure 18. supply current vs. supply voltage 0 0.1 0.2 0.3 0.4 0.5 i dd ( a) 3.5 4.0 2.5 3.0 4.5 5.0 5.5 v dd (v) +25 c ?40 c +105 c 02066-019 figure 19. power-down current vs. supply voltage 0 50 100 150 200 250 i dd ( a) 300 350 400 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 v logic (v) t a = 25 c v dd = 5v v dd = 3v decreasing increasing increasing decreasing 02066-020 figure 20. supply current vs. logic input voltage for sda and scl voltage increasing and decreasing t a = 25 c v dd = 5v v ref = 5v v out a scl c h1 ch1 1v, ch2 5v, time base = 1 s/div c h2 02066-021 figure 21. half-scale settling (1/4 to 3/4 scale code change) t a = 25 c v dd = 5v v ref = 2v v out a v dd c h1 c h2 ch1 2v, ch2 200mv, time base = 200 s/div 02066-022 figure 22. power-on reset to 0 v t a = 25 c v dd = 5v v ref = 2v v out a pd c h1 ch1 500mv, ch2 5v, time base = 1 s/div c h2 02066-023 figure 23. exiting power-down to midscale
ad5306/ad5316/ad5326 rev. f | page 14 of 24 v dd = 5v frequency i dd ( a) 350 400 450 500 550 600 v dd = 3v 02066-0-024 figure 24. i dd histogram with v dd = 3 v and v dd = 5 v v out (v) 2.47 2.49 2.48 2.50 1 s/div 02066-025 figure 25. ad5326 major code transition glitch energy ?60 ?50 ?40 ?30 ?20 ?10 0 10 db 1k 10k 10 100 100k 1m 10m frequency (hz) 02066-026 figure 26. multiplying bandwidth (small-signal frequency response) full-scale error (v) ?0.02 ?0.01 0 0.01 0.02 23 01 456 v ref (v) t a = 25 c v dd = 5v 02066-027 figure 27. full-scale error vs. v ref 1mv/div 50ns/div 02066-028 figure 28. dac-to-dac crosstalk
ad5306/ad5316/ad5326 rev. f | page 15 of 24 functional description the ad5306/ad5316/ad5326 are quad resistor-string dacs fabricated on a cmos process with resolutions of 8, 10, and 12 bits, respectively. each contains four output buffer amplifiers and is written to via a 2-wire serial interface. they operate from single supplies of 2.5 v to 5.5 v, and the output buffer amplifiers provide rail-to-rail output swing with a slew rate of 0.7 v/s. each dac is provided with a separate reference input, which can be buffered to draw virtually no current from the reference source, or unbuffered to give a reference input range from 0.25 v to v dd . the devices have a power-down mode in which all dacs can be turned off completely with a high impedance output. digital-to-analog section the architecture of one dac channel consists of a resistor-string dac followed by an output buffer amplifier. the voltage at the v ref pin provides the reference voltage for the corresponding dac. figure 29 shows a block diagram of the dac architecture. since the input coding to the dac is straight binary, the ideal output voltage is given by n ref out d v v 2 = where: d is the decimal equivalent of the binary code that is loaded to the dac register: 0 to 255 for ad5306 (8 bits) 0 to 1023 for ad5316 (10 bits) 0 to 4095 for ad5326 (12 bits) n is the dac resolution. input register output buffer amplifier reference buffer v out a v ref a buf resistor string dac register 02066-029 figure 29. single dac channel architecture resistor string the resistor string section is shown in figure 30 . it is simply a string of resistors, each of value r. the digital code loaded to the dac register determines at which node on the string the voltage is tapped off to be fed into the output amplifier. the voltage is tapped off by closing one of the switches connecting the string to the amplifier. because it is a string of resistors, it is guaranteed monotonic. dac reference inputs each of the four dacs has a reference pin. the reference inputs are buffered but can also be individually configured as unbuffered. the advantage with the buffered input is the high impedance it presents to the voltage source driving it. however, if the unbuffered mode is used, the user can have a reference voltage as low as 0.25 v and as high as v dd , since there is no restriction due to headroom and footroom of the reference amplifier. r r r r r to output amplifier 02066-030 figure 30. resistor string if there is a buffered reference in the circuit (for example, ref192), there is no need to use the on-chip buffers of the ad5306/ad5316/ad5326. in unbuffered mode, the input impedance is still large at typically 180 k per reference input for 0 v to v ref mode and 90 k for 0 v to 2 v ref mode. the buffered/unbuffered option is controlled by the buf bit in the control byte. the buf bit setting applies to whichever dac is selected in the pointer byte. output amplifier the output buffer amplifier is capable of generating output voltages to within 1 mv of either rail. its actual range depends on the value of v ref , gain, offset error, and gain error. if a gain of 1 is selected (gain = 0), the output range is 0.001 v to v ref . if a gain of 2 is selected (gain = 1), the output range is 0.001 v to 2 v ref . because of clamping, however, the maximum output is limited to v dd C 0.001 v. the output amplifier is capable of driving a load of 2 k to gnd or v dd in parallel with 500 pf to gnd or v dd . the source and sink capabilities of the output amplifier can be seen in the plot in figure 16 . the slew rate is 0.7 v/s with a half-scale settling time to 0.5 lsb (at eight bits) of 6 s.
ad5306/ad5316/ad5326 rev. f | page 16 of 24 power-on reset the ad5306/ad5316/ad5326 have a power-on reset function so that they power up in a defined state. the power-on state is ? normal operation ? reference inputs unbuffered ? 0 v to v ref output range ? output voltage set to 0 v both input and dac registers are filled with 0s and remain so until a valid write sequence is made to the device. this is particularly useful in applications where it is important to know the state of the dac outputs while the device is powering up. serial interface the ad5306/ad5316/ad5326 are controlled via an i 2 c- compatible serial bus. these devices are connected to this bus as slave devices; that is, no clock is generated by the ad5306/ ad5316/ad5326 dacs. this interface is smbus-compatible at v dd < 3.6 v. the ad5306/ad5316/ad5326 has a 7-bit slave address. the five msbs are 00011, and the two lsbs are determined by the state of the a0 and a1 pins. the facility to make hardwired changes to a0 and a1 allows the user to have up to four of these devices on one bus. the 2-wire serial bus protocol operates as follows: 1. the master initiates data transfer by establishing a start condition, which is when a high-to-low transition on the sda line occurs while scl is high. the following byte is the address byte, which consists of the 7-bit slave address followed by an r/ w bit. this bit determines whether data is read from or written to the slave device. the slave whose address corresponds to the transmitted address responds by pulling sda low during the ninth clock pulse (this is termed the acknowledge bit). at this stage, all other devices on the bus remain idle while the selected device waits for data to be written to or read from its shift register. 2. data is transmitted over the serial bus in sequences of nine clock pulses (eight data bits followed by an acknowledge bit). the transitions on the sda line must occur during the low period of scl and remain stable during the high period of scl. 3. when all data bits have been read from or written to, a stop condition is established. in write mode, the master pulls the sda line high during the 10th clock pulse to establish a stop condition. in read mode, the master issues a no acknowledge for the ninth clock pulse; that is, the sda line remains high. the master then brings the sda line low before the 10th clock pulse and then high during the 10th clock pulse to establish a stop condition. read/write sequence for the ad5306/ad5316/ad5326, all write access sequences and most read sequences begin with the device address (with r/ w = 0) followed by the pointer byte. this pointer byte speci- fies the data format and determines that dac is being accessed in the subsequent read/write operation (see figure 1 ). in a write operation, the data follows immediately. in a read operation, the address is resent with r/ w = 1, and the data is then read back. however, it is also possible to perform a read operation by sending only the address with r/ w = 1. the previously loaded pointer settings are then used for the readback operation. dacd x x lsb msb dacc dacb daca 00 02066-031 figure 31. pointer byte pointer byte bits table 6 describes the individual bits that make up the pointer byte. table 6. pointer byte bits bit description x dont care bits. 0 reserved bits. must be set to 0. dacd 1: the following data bytes are for dac d. dacc 1: the following data bytes are for dac c. dacb 1: the following data bytes are for dac b. daca 1: the following data bytes are for dac a. input shift register the input shift register is 16 bits wide. data is loaded into the device as two data bytes on the serial data line, sda, under the control of the serial clock input, scl. the timing diagram for this operation is shown in figure 2 . the two data bytes consist of four control bits followed by 8, 10, or 12 bits of dac data, depending on the device type. the first bits loaded are the control bits: gain, buf, clr , and pd ; the remaining bits are left-justified dac data bits, starting with the msb (see figure 32 ). table 7. input shift register control bits bit description gain 0: output range for that dac set at 0 v to v ref . 1: output range for that dac set at 0 v to 2 v ref . buf 0: reference input for that dac is unbuffered. 1: reference input for that dac is buffered. clr 0: all dac registers and input registers are filled with 0s on completion of the write sequence. 1: normal operation. pd 0: on completion of the write sequence, all four dacs go into power-down mode. the dac outputs enter a high impedance state. 1: normal operation.
ad5306/ad5316/ad5326 rev. f | page 17 of 24 default readback conditions all pointer byte bits power up to 0. therefore, if the user initiates a readback without first writing to the pointer byte, no single dac channel has been specified. in this case, the default readback bits are all 0 except for the clr bit and the pd bit, which are 1. multiple dac write sequence because there are individual bits in the pointer byte for each dac, it is possible to write the same data and control bits to two, three, or four dacs simultaneously by setting the relevant bits to 1. multiple dac readback sequence if the user attempts to read back data from more than one dac at a time, the part reads back the power-on condition of gain, buf, and data bits (all 0), and the current state of clr and pd . 02066-032 buf clr pd d7 d6 d5 d4 gain lsb msb 8-bit ad5306 clr d9 d8 d7 d6 d11 d10 d9 d8 most significant data byte lsb msb 10-bit ad5316 lsb msb 12-bit ad5326 clr least significant data byte d3 d2 d1 d0 0 d5 d4 d3 d2 d1 d0 0 0 d7 d6 d5 d4 d3 d2 d1 d0 lsb msb 8-bit ad5306 lsb msb 10-bit ad5316 lsb msb 12-bit ad5326 000 buf pd gain buf pd gain figure 32. data formats for write and readback
ad5306/ad5316/ad5326 rev. f | page 18 of 24 write operation when writing to the ad5306/ad5316/ad5326 dacs, the user must begin with an address byte (r/ w = 0), after which the dac acknowledges that it is prepared to receive data by pulling sda low. this address byte is followed by the pointer byte, which is also acknowledged by the dac. two bytes of data are then written to the dac, as shown in figure 33 . a stop condition follows. read operation when reading data back from the ad5306/ad5316/ad5326 dacs, the user begins with an address byte (r/ w = 0), after which the dac acknowledges that it is prepared to receive data by pulling sda low. this address byte is usually followed by the pointer byte, which is also acknowledged by the dac. following this, there is a repeated start condition by the master, and the address is resent with r/ w = 1. this is acknowledged by the dac, indicating that it is prepared to transmit data. two bytes of data are then read from the dac, as shown in figure 34 . a stop condition follows. a1 x lsb x r/w a0 0 least significant data byte most significant data byte 00 11 ack by ad53x6 ack by ad53x6 ack by ad53x6 ack by ad533x msb address byte pointer byte start condition by master stop condition by master scl sda scl sda msb lsb msb lsb 02066-033 figure 33. write sequence 02066-034 data byte least significant data byte scl sda msb scl sda msb address byte scl sda msb lsb pointer byte address byte lsb ack by ad53x6 ack by ad53x6 ack by ad53x6 ack by master start condition by master repeated start condition by master no ack by master stop condition by master xx r/w 0 00 11 a1 r/w a0 a1 a0 00 0 11 lsb figure 34. readback sequence
ad5306/ad5316/ad5326 rev. f | page 19 of 24 however, if the master sends an ack and continues clocking scl (no stop is sent), the dac retransmits the same two bytes of data on sda. this allows continuous readback of data from the selected dac register. alternatively, the user can send a start followed by the address with r/ w = 1. in this case, the previously loaded pointer settings are used and readback of data can start immediately. double-buffered interface the ad5306/ad5316/ad5326 dacs have double-buffered interfaces consisting of two banks of registers: input registers and dac registers. the input registers are connected directly to the input shift register and the digital code is transferred to the relevant input register on completion of a valid write sequence. the dac registers contain the digital code used by the resistor strings. access to the dac registers is controlled by the ldac pin. when ldac is high, the dac registers are latched and the input registers can change state without affecting the contents of the dac registers. when ldac is low, however, the dac registers become transparent and the contents of the input registers are transferred to them. double-buffering is useful if the user requires simultaneous updating of all dac outputs. the user may write to each of the input registers individually and then, by pulsing the ldac input low, all outputs update simultaneously. these parts contain an extra feature whereby a dac register is not updated unless its input register has been updated since the last time that ldac was low. normally, when ldac is low, the dac registers are filled with the contents of the input registers. in the ad5306/ad5316/ad5326, the part updates the dac register only if the input register has been changed since the last time the dac register was updated, thereby removing unnecessary digital crosstalk. load dac input ldac ldac transfers data from the input registers to the dac registers and, therefore, updates the outputs. the ldac function enables double-buffering of the dac data, gain, and buf. there are two ldac modes: synchronous mode and asynchronous mode. in synchronous mode, the dac registers are updated after new data is read in on the rising edge of the eighth scl pulse. ldac can be tied permanently low or pulsed as in figure 2 . in asynchronous mode, the outputs are not updated at the same time the input registers are written to. when ldac goes low, the dac registers are updated with the contents of the input registers. power-down mode the ad5306/ad5316/ad5326 have very low power consump- tion, dissipating typically at 1.2 mw with a 3 v supply and 2.5 mw with a 5 v supply. power consumption can be reduced further when the dacs are not in use by putting them into power-down mode, which is selected by setting the pd pin low or by setting bit 12 ( pd ) of the data-word to 0. when the pd pin is high and the pd bit is set to 1, all dacs work normally with a typical power consumption of 500 a at 5 v (400 a at 3 v). in power-down mode, however, the supply current falls to 300 na at 5 v (90 na at 3 v) when all dacs are powered down. not only does the supply current drop, but each output stage is internally switched from the output of its ampli- fier, making it open-circuit. this has the advantage that the outputs are three-state while the part is in power-down mode and provides a defined input condition for whatever is connected to the output of the dac amplifiers. the output stage is shown in figure 35 . power-down circuitry resistor string dac 02066-035 amplifier v out figure 35. output stage during power-down the bias generator, output amplifiers, resistor strings, and all other associated linear circuitry are shut down when power- down mode is activated. however, the contents of the registers are unaffected when in power-down. in fact, it is possible to load new data into the input registers and dac registers during power-down. the dac outputs update as soon as the pd pin goes high or the pd bit is reset to 1. the time to exit power- down is typically 2.5 s for v dd = 5 v and 5 s for v dd = 3 v. this is the time from the rising edge of the eighth scl pulse or from the rising edge of pd to when the output voltage deviates from its power-down voltage (see figure 23 ).
ad5306/ad5316/ad5326 rev. f | page 20 of 24 applications typical application circuit the ad5306/ad5316/ad5326 can be used with a wide range of reference voltages where the devices offer full one-quadrant multiplying capability over a reference range of 0 v to v dd . more typically, these devices are used with a fixed precision- reference voltage. suitable references for 5 v operation are the ad780 and ref192 (2.5 v references). for 2.5 v operation, a suitable external reference is the ad589, a 1.23 v band gap reference. figure 36 shows a typical setup for the ad5306/ ad5316/ad5326 when using an external reference. note that a0 and a1 can be high or low. ad5306/ ad5316/ ad5326 gnd sda serial interface v out ext ref 0.1 f v ref a v ref c v ref d v ref b ad780/ref192 with v dd = 5v or ad599 with v dd = 2.5v v dd = 2.5v to 5.5v v in a0 a1 10 f 1 f scl v out a v out c v out b v out d 02066-036 figure 36. ad5306/ad5316/ad5326 using a 2.5 v external reference driving v dd from the reference voltage if an output range of 0 v to v dd is required when the reference inputs are configured as unbuffered, the simplest solution is to connect the reference inputs to v dd . because this supply may be noisy and somewhat inaccurate, the ad5306/ad5316/ad5326 may be powered from the reference voltage, for example, using a 5 v reference such as the ref195. the ref195 outputs a steady supply voltage for the ad5306/ad5316/ad5326. the typical current required from the ref195 is 500 a supply current and approximately 112 a to supply the reference inputs, if unbuffered. this is with no load on the dac outputs. when the dac outputs are loaded, the ref195 also needs to supply the current to the loads. the total current required (with a 10 k load on each output) is 612 a + (5 v/10 k) = 2.6 ma the load regulation of the ref195 is typically 2 ppm/ma, which results in an error of 5.2 ppm (26 v) for the 2.6 ma current drawn from it. this corresponds to a 0.0013 lsb error at eight bits and a 0.021 lsb error at 12 bits. bipolar operation using the ad5306/ad5316/ad5326 the ad5306/ad5316/ad5326 are designed for single-supply operation, but a bipolar output range is also possible using the circuit in figure 37 . this circuit gives an output voltage range of 5 v. rail-to-rail operation at the amplifier output is achievable using an ad820 or an op295 as the output amplifier. +5v ?5v ad820/ op295 10 f 6v to 12v 0.1 f r1 10k 5v r2 10k a1 a0 g n d v out ad1585 +5v 2-wire serial interface sc l sd a gnd 1 f ad5306/ ad5316/ ad5326 v ref a v ref c v ref d v ref b v out c v out b v out a v out d v in v dd 03756-a-037 figure 37. bipolar operation with the ad5306/ad5316/ad5326 the output voltage for any input code can be calculated as follows: ( ) () () 12 2 r/rrefin r1 r2r1 n /drefin out v ? + = ? ? ? ? ? ? ? ? where: d is the decimal equivalent of the code loaded to the dac. n is the dac resolution. refin is the reference voltage input. with refin = 5 v, r1 = r2 = 10 k, v out = (10 d /2 n ) ? 5 v multiple devices on one bus figure 38 shows four ad5306 devices on the same serial bus. each has a different slave address since the states of the a0 and a1 pins are different. this allows each of 16 dacs to be written to or read from independently. 02066-038 pull-up resistors scl sda ad5306 ad5306 scl sda a0 a1 v dd v dd v dd master a0 a1 scl sda ad5306 ad5306 scl sda a0 a1 a0 a1 figure 38. multiple ad5306 devices on one bus
ad5306/ad5316/ad5326 rev. f | page 21 of 24 ad5306/ad5316/ad5326 as a digitally programmable window detector a digitally programmable upper/lower limit detector using two of the dacs in the ad5306/ad5316/ad5326 is shown in figure 39 . the upper and lower limits for the test are loaded to dacs a and b, which, in turn, set the limits on the cmp04. if the signal at the v in input is not within the programmed window, an led indicates the fail condition. similarly, dac c and dac d can be used for window detection on a second v in signal. 02066-039 v dd 5v gnd v in pass/fail 1/2 cmp04 1/6 74hc05 fail pass 1k 0.1 f scl sda scl din 1k v ref 1 additional pins omitted for clarity 10 f 1/2 ad5306/ ad5316/ ad5326 1 v ref a v ref b v out b v out a figure 39. window detection coarse and fine adjustment using the ad5306/ad5316/ad5326 two of the dacs in the ad5306/ad5316/ad5326 can be paired together to form a coarse and fine adjustment function, as shown in figure 40 . dac a is used to provide the coarse adjustment while dac b provides the fine adjustment. varying the ratio of r1 and r2 changes the relative effect of the coarse and fine adjustments. with the resistor values and external reference shown, the output amplifier has unity gain for the dac a output; therefore, the output range is 0 v to 2.5 v ? 1 lsb. for dac b, the amplifier has a gain of 7.6 10 ?3 , giving dac b a range of 19 mv. similarly, dac c and dac d can be paired together for coarse and fine adjustment. the circuit in figure 40 is shown with a 2.5 v reference, but reference voltages up to v dd may be used. the op amps indicated allow a rail-to-rail output swing. 02066-040 1 f v ref a v dd gnd v out b 0.1 f 10 f vout v in gnd ext ref ad820/ op295 5v r3 51.2k r4 390 ad780/ref192 w ith v dd = 5v v out a r1 390 r2 51.2k v out v dd = 5v 1/2 ad5306/ ad5316/ ad5326 v ref b figure 40. coarse/fine adjustment
ad5306/ad5316/ad5326 rev. f | page 22 of 24 power supply decoupling in any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. the printed circuit board on which the ad5306/ad5316/ad5326 is mounted should be designed so the analog and digital sections are separated and confined to certain areas of the board. if the ad5306/ad5316/ad5326 is in a system where multiple devices require an agnd-to-dgnd connection, the connection should be made at one point only. the star ground point should be established as close as possible to the device. the ad5306/ ad5316/ad5326 should have ample supply bypassing of 10 f in parallel with 0.1 f on the supply located as close to the package as possible, ideally right up against the device. the 10 f capacitors are the tantalum bead type. the 0.1 f capacitor should have low effective series resistance (esr) and low effective series inductance (esi), like the common ceramic types that provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching. the power supply lines of the ad5306/ad5316/ad5326 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. components with fast-switching signals, such as clocks, should be shielded with digital ground to avoid radiating noise to other parts of the board, and they should never be run near the reference inputs. a ground line routed between the sda and scl lines helps to reduce crosstalk between them. although a ground line is not required on a multilayer board because there is a separate ground plane, separating the lines helps. avoid crossover of digital and analog signals. traces on opposite sides of the board should run at right angles to each other. this reduces the effects of feedthrough through the board. a micro- strip technique is the best method, but its use is not always possible with a double-sided board. in this technique, the component side of the board is dedicated to ground plane while signal traces are placed on the solder side. table 8. overview of ad53xx serial devices 1 part no. resolution no. of dacs dnl interface settling time (s) package pins singles ad5300 8 1 0.25 spi 4 sot-23, msop 6, 8 ad5310 10 1 0.5 spi 6 sot-23, msop 6, 8 ad5320 12 1 1.0 spi 8 sot-23, msop 6, 8 ad5301 8 1 0.25 2-wire 6 sot-23, msop 6, 8 ad5311 10 1 0.5 2-wire 7 sot-23, msop 6, 8 ad5321 12 1 1.0 2-wire 8 sot-23, msop 6, 8 duals ad5302 8 2 0.25 spi 6 msop 8 ad5312 10 2 0.5 spi 7 msop 8 ad5322 12 2 1.0 spi 8 msop 8 ad5303 8 2 0.25 spi 6 tssop 16 ad5313 10 2 0.5 spi 7 tssop 16 ad5323 12 2 1.0 spi 8 tssop 16 quads ad5304 8 4 0.25 spi 6 msop 10 ad5314 10 4 0.5 spi 7 msop 10 ad5324 12 4 1.0 spi 8 msop 10 ad5305 8 4 0.25 2-wire 6 msop 10 ad5315 10 4 0.5 2-wire 7 msop 10 ad5325 12 4 1.0 2-wire 8 msop 10 ad5306 8 4 0.25 2-wire 6 tssop 16 ad5316 10 4 0.5 2-wire 7 tssop 16 ad5326 12 4 1.0 2-wire 8 tssop 16 ad5307 8 4 0.25 spi 6 tssop 16 ad5317 10 4 0.5 spi 7 tssop 16 ad5327 12 4 1.0 spi 8 tssop 16 octals ad5308 8 8 0.25 spi 6 tssop 16 ad5318 10 8 0.5 spi 7 tssop 16 ad5328 12 8 1.0 spi 8 tssop 16 1 visit www.analog.com/support/sta ndard_linear/selection _guides/ad53xx.html for more information.
ad5306/ad5316/ad5326 rev. f | page 23 of 24 table 9. overview of ad53xx parallel devices part no. resolution dnl v ref pins settling time (s) additional pin functions package pins singles buf gain hben clr ad5330 8 0.25 1 6 yes yes yes tssop 20 ad5331 10 0.5 1 7 yes yes tssop 20 ad5340 12 1.0 1 8 yes yes yes tssop 24 ad5341 12 1.0 1 8 yes yes yes yes tssop 20 duals ad5332 8 0.25 2 6 yes tssop 20 ad5333 10 0.5 2 7 yes yes yes tssop 24 ad5342 12 1.0 2 8 yes yes yes tssop 28 ad5343 12 1.0 1 8 yes yes tssop 20 quads ad5334 8 0.25 2 6 yes yes tssop 24 ad5335 10 0.5 2 7 yes yes tssop 24 ad5336 10 0.5 4 7 yes yes tssop 28 ad5344 12 1.0 4 8 tssop 28
ad5306/ad5316/ad5326 rev. f | page 24 of 24 outline dimensions 16 9 8 1 pin 1 seating plane 8 0 4.50 4.40 4.30 6.40 bsc 5.10 5.00 4.90 0.65 bsc 0.15 0.05 1.20 max 0.20 0.09 0.75 0.60 0.45 0.30 0.19 coplanarity 0.10 compliant to jedec standards mo-153-ab figure 41. 16-lead thin shrink small outline package [tssop] (ru-16) dimensions shown in millimeters ordering guide model temperature range package description package option ad5306aru ?40c to +105c 16-lead tssop ru-16 ad5306aru-reel7 ?40c to +105c 16-lead tssop ru-16 ad5306aruz 1 ?40c to +105c 16-lead tssop ru-16 ad5306aruz-reel7 1 ?40c to +105c 16-lead tssop ru-16 ad5306bru ?40c to +105c 16-lead tssop ru-16 ad5306bru-reel ?40c to + 105c 16-lead tssop ru-16 ad5306bru-reel7 ?40c to + 105c 16-lead tssop ru-16 ad5306bruz 1 ?40c to +105c 16-lead tssop ru-16 AD5306BRUZ-REEL 1 ?40c to +105c 16-lead tssop ru-16 AD5306BRUZ-REEL7 1 ?40c to +105c 16-lead tssop ru-16 ad5316aru ?40c to +105c 16-lead tssop ru-16 ad5316aru-reel7 ?40c to +105c 16-lead tssop ru-16 ad5316aruz 1 ?40c to +105c 16-lead tssop ru-16 ad5316bru ?40c to +105c 16-lead tssop ru-16 ad5316bru-reel ?40c to + 105c 16-lead tssop ru-16 ad5316bru-reel7 ?40c to + 105c 16-lead tssop ru-16 ad5316bruz 1 ?40c to +105c 16-lead tssop ru-16 ad5316bruz-reel 1 ?40c to +105c 16-lead tssop ru-16 ad5316bruz-reel7 1 ?40c to +105c 16-lead tssop ru-16 ad5326aru ?40c to +105c 16-lead tssop ru-16 ad5326aru-reel7 ?40c to +105c 16-lead tssop ru-16 ad5326aruz 1 ?40c to +105c 16-lead tssop ru-16 ad5326bru ?40c to +105c 16-lead tssop ru-16 ad5326bru-reel ?40c to + 105c 16-lead tssop ru-16 ad5326bru-reel7 ?40c to + 105c 16-lead tssop ru-16 ad5326bruz 1 ?40c to +105c 16-lead tssop ru-16 ad5326bruz-reel 1 ?40c to +105c 16-lead tssop ru-16 ad5326bruz-reel7 1 ?40c to +105c 16-lead tssop ru-16 1 z = pb-free part. ? 2005 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. c02066C0C8/05(f)

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